In a semiconductor memory such a ferroelectric memory, a plate line is commonly coupled to ferroelectric capacitors in plural memory cells, and the load capacity of the plate line is large. Because of those features, a waveform of a signal transmitted in the plate line may be rounded and a drive time using such a plate line may become longer. As a result, access time of the memory cell may be extended. To reduce the load capacity of the plate line, there is a known method of dividing the plate line into plural plate-line segments to reduce the number of memory cells coupled to each of the divided plural plate-line segments (see, for example, Japanese Laid-open Patent Publication No. 10-229171).
However, when the plate line is divided as such, the number of plate lines is accordingly increased. As a result, a scale of the logic circuit to select the plate lines may become larger, and accordingly the chip size of the semiconductor memory may become larger.